Azuro
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'''Azuro, Inc.''' is an [[electronic design automation]] (EDA) [[software]] company. It is headquartered in [[Santa Clara, California]] with a development office in [[Cambridge]], UK.
Azuro develops software for the design of [[integrated circuit]]s, specializing in analyzing power consumption of the chips.
To produce more efficient chips Azuro has developed a program called ''PowerCentric''<ref>[http://www.highbeam.com/doc/1P1-126612580.html Azuro Rolls Out PowerCentric for ARC Configurable Subsystems and Cores]</ref> by concentrating on the [[Clock Distribution Networks|clock network]]. In [[synchronous circuit]] designs all changes of [[State (computer science)|state]] are coordinated by a [[Clock signal|clock]], and this clock edge must be distributed to all parts of the chip. Since the clock signal is distributed throughout the entire circuit it can consume a large percentage of the energy used. Azuro's approach unifies the steps of clock gating and clock tree synthesis. Azuro has a patent pending on a technique it calls iCTS for doing this.
== See also ==
*[[Electronic design automation]]
*[[Design flow (EDA)]]
*[[Integrated circuit design]]
== References ==
<references />
*[http://eetimes.com/news/design/showArticle.jhtml?articleID=190300222 EETimes: Power reduction tool extends to 65-nm]
*[http://www.eetimes.com/news/design/showArticle.jhtml?articleID=202804213 EETimes: Starc adopts Azuro's clock-tree synthesis].
*[http://www.edn.com/article/CA6349775.html EDN: Azuro Cuts Power in 65nm Digital Designs ]
*[http://www.edn.com/article/CA601818.html EDN: Power-savvy tool replaces clock-tree synthesis]
*[http://www.eetimes.eu/163104557 EETimes Europe: Startup targets power problems in wireless IC design]
[[Category:Electronic design automation companies]]