Flash memory
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Reverted edits by [[Special:Contributions/123.243.27.198|123.243.27.198]] to last version by Dspark76 (using [[WP:HG|Huggle]])
{{Refimprove|date=April 2008}}
{{Memory types}}
[[Image:DSCN0411.JPG|thumb|right|A [[USB flash drive]]. The chip on the left is the flash memory. The [[microcontroller]] is on the right.]]
'''Flash memory''' is [[non-volatile memory|non-volatile]] [[computer storage|computer memory]] that can be electrically erased and reprogrammed. It is a technology that is primarily used in [[memory card]]s and [[USB flash drive]]s for general storage and transfer of data between computers and other digital products. It is a specific type of [[EEPROM]] (Electrically Erasable Programmable Read-Only Memory) that is erased and programmed in large blocks; in early flash the entire chip had to be erased at once. Flash memory costs far less than byte-programmable EEPROM and therefore has become the dominant technology wherever a significant amount of non-volatile, [[solid-state]] storage is needed. Example applications include [[Personal digital assistant|PDA]]s (personal digital assistants), laptop computers, [[digital audio player]]s, [[digital camera]]s and [[mobile phone]]s. It has also gained popularity in the game console market, where it is often used instead of [[EEPROM]]s or battery-powered [[static RAM|SRAM]] for game save data.
Flash memory is [[non-volatile memory|non-volatile]], which means that no power is needed to maintain the information stored in the chip. In addition, flash memory offers fast read [[access time]]s (although not as fast as volatile [[dynamic random access memory|DRAM]] memory used for main memory in PCs) and better kinetic shock resistance than [[hard disk]]s. These characteristics explain the popularity of flash memory in portable devices. Another feature of flash memory is that when packaged in a "memory card," it is enormously durable, being able to withstand intense pressure, extremes of temperature, and even immersion in water.
Although technically a type of [[EEPROM]], the term "[[EEPROM]]" is generally used to refer specifically to non-flash EEPROM which is erasable in small blocks, typically bytes. Because erase cycles are slow, the large block sizes used in flash memory erasing give it a significant speed advantage over old-style [[EEPROM]] when writing large amounts of data.
==History==
Flash memory (both NOR and NAND types) was invented by Dr. [[Fujio Masuoka]] while working for [[Toshiba]] circa 1980.<ref>{{cite web|last=Fulford|first=Benjamin|title=Unsung hero|publisher=Forbes|date=24 June 2002|accessdate=2008-03-18|url=http://www.forbes.com/global/2002/0624/030.html}}</ref><ref>{{patent|US|4531203|Fujio Masuoka}}</ref> According to Toshiba, the name "flash" was suggested by Dr. Masuoka's colleague, Mr. Shoji Ariizumi, because the erasure process of the memory contents reminded him of a [[flash (photography)|flash]] of a camera. Dr. Masuoka presented the invention at the [[IEEE]] 1984 International Electron Devices Meeting (IEDM) held in San Francisco, California.
[[Intel]] saw the massive potential of the invention and introduced the first commercial NOR type flash chip in 1988.<ref>{{citeweb |url=http://www2.electronicproducts.com/NAND_vs_NOR_flash_technology-article-FEBMSY1-FEB2002.aspx |title=NAND vs. NOR flash technology: The designer should weigh the options when using flash memory |LAST=Tal |first=Arie |date= Feb 2002 |accessdate=2008-07-11}}</ref> NOR-based flash has long erase and write times, but provides full address and data buses, allowing [[random access]] to any memory location. This makes it a suitable replacement for older [[Read-only memory|ROM]] chips, which are used to store program code that rarely needs to be updated, such as a computer's [[BIOS]] or the [[firmware]] of [[set-top box]]es. Its endurance is 10,000 to 1,000,000 erase cycles.{{Fact|date=April 2007}} NOR-based flash was the basis of early flash-based removable media; [[CompactFlash]] was originally based on it, though later cards moved to less expensive NAND flash.
[[Toshiba]] announced NAND flash at [[ISSCC]] in 1989. It has faster erase and write times, and requires a smaller chip area per cell, thus allowing greater storage densities and lower costs per bit than NOR flash; it also has up to ten times the endurance of NOR flash. However, the I/O interface of NAND flash does not provide a random-access external address bus. Rather, data must be read on a block-wise basis, with typical block sizes of hundreds to thousands of bits. This made NAND flash unsuitable as a drop-in replacement for program ROM since most microprocessors and microcontrollers required byte-level random access. In this regard NAND flash is similar to other [[secondary storage]] devices such as [[hard disk]]s and [[optical media]], and is thus very suitable for use in mass-storage devices such as [[memory card]]s. The first NAND-based removable media format was [[SmartMedia]], and many others have followed, including [[MultiMediaCard]], [[Secure Digital]], [[Memory Stick]] and [[xD-Picture Card]]. A new generation of memory card formats, including [[RS-MMC]], [[miniSD]] and [[microSD]], and [[Intelligent Stick]], feature extremely small form factors. For example, the microSD card has an area of just over 1.5 cm², with a thickness of less than 1 mm; microSD capacities range from 64MB to 16GB, as of [[March 2008]]. {{Fact|date=April 2008}}
==Principles of operation==
Flash memory stores information in an array of memory cells made from [[floating-gate transistor]]s. In traditional [[single-level cell]] ('''SLC''') devices, each cell stores only one bit of information. Some newer flash memory, known as
[[multi-level cell]] ('''MLC''') devices, can store more than one bit per cell by choosing between multiple levels of electrical charge to apply to the floating gates of its cells.
[[Image:Flash cell structure.svg|thumb|right|A flash memory cell.]]
===NOR flash===
[[Image:Flash-Programming.svg|thumb|left|Programming a NOR memory cell (setting it to logical 0), via hot-electron injection.]]
[[Image:Flash erase.svg|thumb|left|Erasing a NOR memory cell (setting it to logical 1), via quantum tunneling.]]
In [[NOR gate]] flash, each cell resembles a standard [[MOSFET]], except the transistor has two gates instead of one. On top is the control gate (CG), as in other MOS transistors, but below this there is a floating gate (FG) insulated all around by an [[oxide]] layer. The FG is interposed between the CG and the [[MOSFET]] channel. Because the FG is electrically isolated by its insulating layer, any [[electron]]s placed on it are trapped there and, under normal conditions, will not discharge for many years. When the FG holds a charge, it [[electric field screening|screens]] (partially cancels) the [[electric field]] from the CG, which modifies the [[threshold voltage]] (V<sub>T</sub>) of the cell. During read-out, a [[voltage]] is applied to the CG, and the MOSFET channel will become conducting or remain insulating, depending on the V<sub>T</sub> of the cell, which is in turn controlled by charge on the FG. The current flow through the MOSFET channel is sensed and forms a [[binary code]], reproducing the stored [[data]]. In a multi-level cell device, which stores more than one [[bit]] per cell, the ''amount'' of current flow is sensed (rather than simply its presence or absence), in order to determine more precisely the level of charge on the FG.
A single-level NOR flash cell in its default state is logically equivalent to a binary "1" value, because current will flow through the channel under application of an appropriate voltage to the control gate. A NOR flash cell can be programmed, or set to a binary "0" value, by the following procedure:
* an elevated on-voltage (typically >5 V) is applied to the CG
* the channel is now turned on, so electrons can flow from the source to the drain (assuming an NMOS transistor)
* the source-drain current is sufficiently high to cause some high energy electrons to jump through the insulating layer onto the FG, via a process called [[hot carrier injection|hot-electron injection]]
To erase a NOR flash cell (resetting it to the "1" state), a large voltage ''of the opposite polarity'' is applied between the CG and drain, pulling the electrons off the FG through [[quantum tunneling]]. Modern NOR flash memory chips are divided into erase segments (often called blocks or sectors). The erase operation can only be performed on a block-wise basis; all the cells in an erase segment must be erased together. Programming of NOR cells, however, can generally be performed one byte or word at a time.
Despite the need for high programming and erasing voltages, virtually all flash chips today require only a single supply voltage, and produce the high voltages via on-chip [[charge pump]]s.
[[Image:NOR flash layout.svg|thumb|right|NOR flash memory wiring and structure on silicon]]
===NAND flash===
[[Sheffer stroke#NAND gate|NAND gate]] flash uses [[tunnel injection]] for writing and [[tunnel release]] for erasing. NAND flash memory forms the core of the removable [[Universal Serial Bus|USB]] storage devices known as [[USB flash drive]]s, as well as most [[memory card]] formats available today.
[[Image:Nand flash structure.svg|thumb|left|NAND flash memory wiring and structure on silicon]]
==Industry==
One source states that, in 2008, the flash memory industry includes about US$9.1 billion in production and sales. [[Apple Inc.]] is the third largest purchaser of flash memory, consuming about 13% of production by itself.<ref>{{cite journal |last=Deffree |first=Suzanne |year=2008 |month=4|title=Apple sneezes, flash industry gets sick |journal=EDN |volume=2008 |issue=7 |pages=74 |accessdate= 2008-04-19 |url=http://www.edn.com/index.asp?layout=article&articleid=CA6544754}}</ref> Other sources put the flash memory market at a size of more than US$20 billion dollars in 2006, accounting for more than eight percent of the overall semiconductor market and more than 34 percent of the total semiconductor memory market.<ref>
{{cite journal |last=Yinug |first=Christopher Falan |year=2007 |month=7 |title=The Rise of the Flash Memory Market: Its Impact on Firm Behavior and Global Semiconductor Trade Patterns |journal=Journal of International Commerce and Economics|url=http://www.usitc.gov/journal/Final_falan_article1.pdf |accessdate= 2008-04-19 }}</ref>
==Limitations==
===Block erasure===
One limitation of flash memory is that although it can be read or programmed a byte or a word at a time in a random access fashion, it must be erased a "block" at a time. This generally sets all bits in the block to 1. Starting with a freshly erased block, any location within that block can be programmed. However, once a bit has been set to 0, only by erasing the entire block can it be changed back to 1. In other words, flash memory (specifically NOR flash) offers random-access read and programming operations, but cannot offer arbitrary random-access rewrite or erase operations. A location can, however, be rewritten as long as the new value's 0 bits are a superset of the over-written value's. For example, a [[nibble]] value may be erased to 1111, then written as 1110. Successive writes to that nibble can change it to 1010, then 0010, and finally 0000. In practice few algorithms can take advantage of this successive write capability and in general the entire block is erased and rewritten at once.
Although data structures in flash memory cannot be updated in completely general ways, this allows members to be "removed" by marking them as invalid. This technique must be modified somewhat for multi-level devices, where one memory cell holds more than one bit.
===Memory wear===
Another limitation is that flash memory has a finite number of erase-write cycles (most commercially available flash products are guaranteed to withstand 100,000 write-erase-cycles for block 0, and no guarantees for other blocks).<ref>{{cite web|url=http://lwn.net/Articles/234441/|title=lwn.net/Articles/234441/<!--INSERT TITLE-->}}</ref> This effect is partially offset by some chip firmware or file system drivers by counting the writes and dynamically remapping the blocks in order to spread the write operations between the sectors; this technique is called [[wear levelling]]. Another approach is to perform write verification and remapping to spare sectors in case of write failure, a technique called bad block management (BBM). For portable consumer devices, these wearout management techniques typically extend the life of the flash memory beyond the life of the device itself, and some data loss may be acceptable in these applications. For high reliability data storage, however, it is not advisable to use flash memory that has been through a large number of programming cycles. This limitation does not apply to 'read-only' applications such as [[thin clients]] and [[routers]], which are only programmed once or at most a few times during their lifetime.
==Low-level access==
The low-level interface to flash memory chips usually differs from those of other common types such as [[DRAM]], [[Read-only memory|ROM]], and [[EEPROM]], which support [[random-access]] via externally accessible [[address bus]]es.
While NOR memory provides an external address bus for read operations (and thus supports random-access), unlocking, erasing, and writing NOR memory must proceed on a block-by-block basis. Typical block sizes are 64, 128, or 256 bytes. With NAND flash memory, ''all'' operations must be performed in a block-wise fashion: reading, unlocking, erasing, and writing.
===NOR memories===
Reading from NOR flash is similar to reading from random-access memory, provided the address and data bus are mapped correctly. Because of this, most microprocessors can use NOR flash memory as [[execute in place]] (XIP) memory, meaning that programs stored in NOR flash can be executed directly without the need to copy them into RAM. NOR flash chips lack intrinsic bad block management, so when a flash block is worn out, the software or [[device driver]] controlling the device must handle this, or the device will cease to work reliably.
When unlocking, erasing or writing NOR memories, special commands are written to the first page of the mapped memory. These commands are defined by the ''[[Common Flash Memory Interface|Common Flash memory Interface]]'' (CFI) and the flash chips can provide a list of available commands to the physical driver.
Apart from being used as random-access ROM, NOR memories can also be used as storage devices. However, NOR flash chips typically have slow write speeds compared with NAND flash.
===NAND memories===<!-- This section is linked from [[Centrino]] -->
NAND flash architecture was introduced by [[Toshiba]] in 1989. These memories are accessed much like [[block size (data storage and transmission)|block devices]] such as [[hard disk]]s or [[memory card]]s. Each block consists of a number of pages. The pages are typically 512 or 2,048 or 4,096 [[byte]]s in size. Associated with each page are a few bytes (typically 12–16 bytes) that should be used for storage of an [[error detection and correction]] [[checksum]].
Typical block sizes include:</br>
32 pages of 512 bytes each for a block size of 16 [[kibibyte|kiB]]</br>
64 pages of 2,048 bytes each for a block size of 128 kiB</br>
64 pages of 4,096 bytes each for a block size of 256 kiB</br>
128 pages of 4,096 bytes each for a block size of 512 kiB
While programming is performed on a page basis, erasure can only be performed on a block basis. Another limitation of NAND flash is data in a block can only be written sequentially. Number of Operations(NOPs) is the number of times the sectors can be programmed. So far this number for MLC flash is always one whereas for SLC flash it is 4.
NAND devices also require [[bad block management]] by the device driver software, or by a separate controller chip. SD cards, for example, include controller circuitry to perform bad block management and [[wear leveling]]. When a logical block is accessed by high-level software, it is mapped to a physical block by the device driver or controller, and a number of blocks on the flash chip are set aside for storing mapping tables to deal with bad blocks. The overall memory capacity gradually shrinks as more blocks are marked as bad.
The error-correcting and detecting [[checksum]] will typically correct an error where one bit per 256 bytes (2,048 [[bit]]s) is incorrect. When this happens, the block is marked bad in a logical block allocation table, and its undamaged contents are copied to a new block and the logical block allocation table is altered accordingly. If more than one bit out of 2,048 is corrupted, the contents are partly lost, i.e. it is no longer possible to reconstruct the original contents. If this is detected when the block is written, the contents may still be available.
Most NAND devices are shipped from the factory with some bad blocks which are typically identified and marked according to a specified bad block marking strategy. By allowing some bad blocks, the manufacturers achieve far higher yields than would be possible if all blocks were tested good. This significantly reduces NAND flash costs and only slightly decreases the storage capacity of the parts.
The first physical block (block 0) is always guaranteed to be readable and free from errors. Hence, all vital pointers for partitioning and bad block management for the device must be located inside this block (typically a pointer to the bad block tables etc). If the device is used for booting a system, this block may contain the [[master boot record]].
When executing software from NAND memories, [[virtual memory]] strategies are often used: memory contents must first be [[paging|paged]] or copied into memory-mapped RAM and executed there. A [[memory management unit]] (MMU) in the system is helpful, but this can also be accomplished with [[overlay (programming)|overlays]]. For this reason, some systems will use a combination of NOR and NAND memories, where a smaller NOR memory is used as software [[read-only memory|ROM]] and a larger NAND memory is partitioned with a [[file system]] for use as a random access storage area. NAND is best suited to flash devices requiring high capacity data storage. This type of flash architecture combines higher storage space with faster erase, write, and read capabilities over the execute in place advantage of the NOR architecture.
===Standardization===
A group called the [[Open NAND Flash Interface Working Group]] (ONFI) has developed a standardized low-level interface for NAND flash chips. This allows interoperability between conforming NAND devices from different vendors. The ONFI specification version 1.0<ref>{{cite web|url=http://www.onfi.org/docs/ONFI_1_0_Gold.pdf|title=www.onfi.org/docs/ONFI_1_0_Gold.pdf<!--INSERT TITLE-->|format=PDF}}</ref> was released on December 28, 2006. It specifies:
* a standard physical interface ([[pinout]]) for NAND flash in [[Thin small-outline package|TSOP]]-48, [[Very very thin small-outline package|WSOP]]-48, [[Land grid array|LGA]]-52, and [[Ball grid array|BGA]]-63 [[IC package|packages]]
* a standard command set for reading, writing, and erasing NAND flash chips
* a mechanism for self-identification (comparable to the [[Serial Presence Detect]]ion feature of [[SDRAM]] chips)
The ONFI group is supported by major NAND flash manufacturers, including [[Intel]], [[Micron Technology]], and [[Sony]], as well as by major manufacturers of devices incorporating NAND flash chips.<ref>A list of ONFI members is available at http://www.onfi.org/onfimembers.html.</ref>
A group of vendors, including Intel, [[Dell]], and [[Microsoft]] formed a Non-Volatile Memory Host Controller Interface (NVMHCI) Working Group.<ref>{{cite web|url=http://www.intel.com/pressroom/archive/releases/20070530corp.htm|title=www.intel.com/pressroom/archive/releases/20070530corp.htm<!--INSERT TITLE-->}}</ref> The goal of the group is to provide standard software and hardware programming interfaces for nonvolatile memory subsystems, including the "[[flash cache]]" device connected to the [[PCI Express]] bus.
==Distinction between NOR and NAND flash==
NOR and NAND flash differ in two important ways:
* the connections of the individual memory cells are different
* the interface provided for reading and writing the memory is different (NOR allows random-access for reading, NAND allows only page access)
It is important to understand that these two are linked by the design choices made in the development of NAND flash. An important goal of NAND flash development was to reduce the chip area required to implement a given capacity of flash memory, and thereby to reduce cost per bit and increase maximum chip capacity so that flash memory could compete with [[magnetic storage]] devices like [[hard disk]]s.
NOR and NAND flash get their names from the structure of the interconnections between memory cells.<ref name="toshibaguide">See pages 5-7 of Toshiba's "NAND Applications Design Guide" under [[#External links|External links]].</ref> In NOR flash, cells are connected in parallel to the [[bitline|bit lines]], allowing cells to be read and programmed individually. The parallel connection of cells resembles the parallel connection of transistors in a CMOS [[NOR]] gate. In NAND flash, cells are connected in series, resembling a [[NAND]] gate, and preventing cells from being read and programmed individually: the cells connected in series must be read in series.
When NOR flash was developed, it was envisioned as a more economical and conveniently rewritable ROM than contemporary [[EPROM]], [[EAROM]], and [[EEPROM]] memories. Thus random-access reading circuitry was necessary. However, it was expected that NOR flash ROM would be read much more often than written, so the write circuitry included was fairly slow and could only erase in a block-wise fashion; random-access write circuitry would add to the complexity and cost unnecessarily.
Because of the series connection, a large grid of NAND flash memory cells will occupy only a small fraction of the area of equivalent NOR cells (assuming the same [[CMOS]] process resolution, e.g. 130 [[nanometer|nm]], 90 nm, 65 nm). NAND flash's designers realized that the area of a NAND chip, and thus the cost, could be further reduced by removing the external address and data bus circuitry. Instead, external devices could communicate with NAND flash via sequential-accessed command and data registers, which would internally retrieve and output the necessary data. This design choice made random-access of NAND flash memory impossible, but the goal of NAND flash was to replace [[hard disk]]s, not to replace ROMs.
===Endurance===
The endurance of SLC Floating Gate NOR flash is typically equal or greater than that of NAND flash while MLC NOR & NAND Flash have similar Endurance capabilities. Example Endurance cycle ratings listed in datasheets for NAND and NOR Flash are provided. NAND Flash is typically rated at ~100K cycles (Samsung OneNAND KFW4G16Q2M), SLC Floating Gate NOR Flash has typical Endrance rating of 100K to 1,000K cycles(Numonyx M58BW 100K Spansion S29CD16J 1000K), while MLC Floating Gate NOR has typical Endurance rating of 100K cycles(Numonyx J3 Flash)
==Serial flash==
Serial flash is a small, low-power flash memory that uses a serial interface, typically [[Serial Peripheral Interface Bus|SPI]], for sequential data access. When incorporated into an [[embedded system]], serial flash requires fewer wires on the [[printed circuit board|PCB]] than parallel flash memories, since it transmits and receives data one bit at a time. This may permit a reduction in board space, power consumption, and total system cost.
There are several reasons why a serial device, with fewer external pins than a parallel device, can significantly reduce overall cost:
* Many [[application-specific integrated circuit|ASICs]] are '''pad-limited''', meaning that the size of the [[die (integrated circuit)|die]] is constrained by the number of [[wire bond]] pads, rather than the complexity and number of gates used for the device logic. Eliminating bond pads thus permits a more compact integrated circuit, on a smaller die; this increases the number of dies that may be fabricated on a [[wafer (electronics)|wafer]], and thus reduces the cost per die.
* Reducing the number of external pins also reduces assembly and [[IC package|packaging]] costs. A serial device may be packaged in a smaller and simpler package than a parallel device.
* Smaller and lower pin-count packages occupy reduced PCB area.
* Lower pin-count devices simplify PCB [[routing (EDA)|routing]].
===Firmware storage===
With the increasing speed of modern CPUs, parallel flash devices are often too slow to [[execute in place]] program code stored on them. Conversely, modern [[Static RAM|SRAM]] offers access times below 10 [[nanosecond|ns]], while [[DDR2 SDRAM|DDR2]] [[SDRAM]] offers access times below 20 ns. Because of this, it is often necessary to [[shadow RAM|shadow]] code stored in flash into RAM; that is, code must be copied from flash into RAM before execution, so that the CPU may access it at full speed. Device [[firmware]] may be stored in a serial flash device, and then copied into SDRAM or SRAM when the device is powered-up.<ref>Many serial flash devices implement a ''bulk read'' mode and incorporate an internal address counter, so that it is trivial to configure them to transfer their entire contents to RAM on power-up. When clocked at 50 MHz, for example, a serial flash could transfer a 64 [[Mbit]] firmware image in less than two seconds.</ref> Using an external serial flash device rather than on-chip flash removes the need for significant process compromise (a process that is good for high speed logic is generally not good for flash and vice-versa). Once it is decided to read the firmware in as one big block it is common to add compression to allow a smaller flash chip to be used. Typical applications for serial flash include storing firmware for [[hard drive]]s, [[Ethernet]] controllers, [[DSL modem]]s, [[wireless card|wireless network devices]], etc.
==Flash file systems==
Because of the particular characteristics of flash memory, it is best used with either a controller to perform [[wear-levelling]] and [[error correction]] or specifically designed [[file system]]s which spread writes over the media and deal with the long erase times of NOR flash blocks. The basic concept behind flash file systems is: When the flash store is to be updated, the file system will write a new copy of the changed data over to a fresh block, remap the file pointers, then erase the old block later when it has time.
One of the earliest flash file systems was [[Microsoft]]'s FFS2 (presumably preceded by FFS1), for use with [[MS-DOS]] in the early 1990s.<ref>[http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=5392427.PN.&OS=PN/5392427&RS=PN/5392427 Microsoft FFS2 patent]</ref>
Around 1994, the [[PCMCIA]], an industry group, approved the '''Flash Translation Layer (FTL)''' specification, which allowed a [[Linear Flash]] device to look like a [[File Allocation Table|FAT]] disk, but still have effective [[wear levelling]]. Other commercial systems such as FlashFX and FlashFX Pro by Datalight were created to avoid patent concerns with FTL.
[[ZFS]] by [[Sun Microsystems]] has been optimized to manage Flash SSD systems, both as cache as well as main storage facilities, available for [[OpenSolaris]], [[Mac OSX]], and the [[Linux]] operating system. Sun has announced a complete line of Flash enabled systems and storage devices.
[[JFFS]] was the first flash-specific file system for [[Linux]], but it was quickly superseded by [[JFFS2]], originally developed for NOR flash. Then [[YAFFS]] was released in 2002, dealing specifically with NAND flash, and [[JFFS2]] was updated to support NAND flash too.
In practice, flash file systems are only used for "[[Memory Technology Device]]s" ("MTD"), which are embedded flash memories that do not have a controller. Removable flash [[memory card]]s and [[USB flash drive]]s have built-in controllers to perform [[wear-levelling]] and [[error correction]] so use of a specific flash file system does not add any benefit. These removable flash memory devices use the [[File Allocation Table|FAT]] file system to allow universal compatibility with computers, cameras, PDAs and other portable devices with memory card slots or ports.
==Capacity==
Multiple chips are often arrayed to achieve higher capacities for use in consumer electronic devices such as [[multimedia player]] or [[GPS]]. The capacity of flash chips generally follows [[Moore's Law]] because they are manufactured with many of the same [[integrated circuits]] techniques and equipment.
Consumer flash drives typically have sizes measured in powers of two (e.g. 512 [[megabyte|MB]], 8 GB), but unlike [[DIMM]]s (and like [[hard drive]]s) these sizes use [[SI prefix|decimal units]].
In 2005, [[Toshiba]] and [[SanDisk]] developed a [[NAND]] flash chip capable of storing 1 [[gigabyte|GB]] of data using [[Multi-level Cell]] (MLC) technology, capable of storing 2 bits of data per cell. In September 2005, [[Samsung Electronics]] announced that it had developed the world’s first 2 GB chip.<ref>{{cite web|url=http://www.xbitlabs.com/news/memory/display/20050912212649.html|title=www.xbitlabs.com/news/memory/display/20050912212649.html<!--INSERT TITLE-->}}</ref>
In March 2006, Samsung announced flash hard drives with a capacity of 4 GB, essentially the same order of magnitude as smaller laptop hard drives, and in September 2006, Samsung announced an 8 GB chip produced using a [[40 nanometer]] [[CMOS|manufacturing process]].<ref>{{cite web|url=http://www.tgdaily.com/content/view/28504/135/|title=www.tgdaily.com/content/view/28504/135/<!--INSERT TITLE-->}}</ref>
In January 2008 [[Sandisk]] announced availability of their 12GB MicroSDHC and 32GB SDHC Plus cards. <ref>[http://www.sandisk.com/Corporate/PressRoom/PressReleases/PressRelease.aspx?ID=4079 12GB MicroSDHC ]</ref><ref>[ http://www.sandisk.com/Corporate/PressRoom/PressReleases/PressRelease.aspx?ID=4091 32GB SDHC Plus]</ref>
==Transfer rates==
Commonly advertised is the maximum read speed, NAND flash memory cards are generally faster at reading than writing.
Transferring multiple small files, smaller than the chip specific block size, could lead to much lower rate.
Access latency has an influence on performance but is less of an issue than with their hard drive counterpart.
Sometimes denoted in MB/s (megabyte per second), or in number of "X" like 60x 100x or 150x. "X" speed rating makes reference to the speed at which a legacy audio CD drive would deliver data, 1x is equal to 150 [[kibibytes]] per second.
For example, a 100x memory card goes to 150 KiB x 100 = 15000 KiB per second = 14.65 MiB per second.<br />
Note that the exact speed depends on whether the marketer means 10<sup>6</sup> bytes or 2<sup>20</sup> bytes by "[[megabyte]]".
==Flash memory as a replacement for hard drives==
{{main|Solid-state drive}}
An obvious extension of flash memory would be as a replacement for [[hard disk]]s. Flash memory does not have the mechanical limitations and latencies of hard drives, so the idea of a [[solid-state drive]], or SSD, is attractive when considering speed, noise, power consumption, and reliability.
There remain some aspects of flash-based SSDs that make the idea unattractive. Most importantly, the cost per gigabyte of flash memory remains significantly higher than that of platter-based hard drives. Although this ratio is decreasing rapidly for flash memory, it is not yet clear that flash memory will catch up to the capacities and affordability offered by platter-based storage. Still, research and development is sufficiently vigorous that it is not clear that it will not happen, either.{{Fact|date=April 2008}}
There is also some concern that the finite number of erase/write cycles of flash memory would render flash memory unable to support an operating system. This seems to be a decreasing issue as warranties on flash-based SSDs are approaching those of current hard drives.<ref>{{cite web|url=http://www.storagesearch.com/semico-art1.html|title=www.storagesearch.com/semico-art1.html<!--INSERT TITLE-->}}</ref><ref>{{cite web|url=http://www.storagesearch.com/bitmicro-art1.html|title=www.storagesearch.com/bitmicro-art1.html<!--INSERT TITLE-->}}</ref>
As of [[May 24]], [[2006]], [[South Korea]]n consumer-electronics manufacturer [[Samsung Electronics]] had released the first flash-memory based PCs, the Q1-SSD and Q30-SSD, both of which have 32 GB SSDs.<ref>{{cite web|url=http://www.samsung.com/he/presscenter/pressrelease/pressrelease_20060524_0000257996.asp|title=www.samsung.com/he/presscenter/pressrelease/pressrelease_20060524_0000257996.asp<!--INSERT TITLE-->}}</ref> Dell Computer introduced the Latitude D430 laptop with 32 GB flash-memory storage in July 2007 -- at a price significantly above a hard-drive equipped version.{{Fact|date=April 2008}}
At the [[Las Vegas metropolitan area|Las Vegas]] [[Consumer Electronics Show|CES 2007]] Summit [[Taiwan]]ese memory company [[A-DATA]] showcased [[Solid-state drive|SSD]] hard disk drives based on Flash technology in capacities of 32 GB, 64 GB and 128 GB.<ref>{{cite web|url=http://www.theinquirer.net/default.aspx?article=36841|title=Future of Flash revealed}}</ref>
Sandisk announced an OEM 32 GB 1.8" SSD drive at CES 2007.<ref>{{cite web|url=http://www.sandisk.com/Oem/Default.aspx?CatID=1477|title=SanDisk SSD Solid State Drives}}</ref> The [[XO-1 (laptop)|XO-1]], developed by the [[OLPC|One Laptop Per Child (OLPC)]] association, uses flash memory rather than a hard drive. As of June 2007, a South Korean company called Mtron claims the fastest SSD with sequential read/write speeds of 100 MB/80 MB per second.<ref>[http://www.mtron.net/eng/index.asp MTRON | Home<!-- Bot generated title -->]</ref>
Rather than entirely replacing the hard drive, hybrid techniques such as [[hybrid drive]] and [[ReadyBoost]] attempt to combine the advantages of both technologies, using flash as a high-speed [[cache]] for files on the disk that are often referenced, but rarely modified, such as application and operating system [[executable]] files. Also, Addonics has a PCI adapter for 4 CF cards,<ref>{{cite web|url=http://www.addonics.com/products/flash_memory_reader/ad4cfprj.asp|title=Addonics PCI adapter for 4 CF cards}}</ref> creating a RAID-able array of solid-state storage that is much cheaper than the hardwired-chips PCI card kind.
The [[ASUS Eee PC]] uses a flash-based SSD of 2GB to 20GB, depending on model. The [[Apple Inc.]] [[Macbook Air]] has the option to upgrade the standard hard drive to a 64GB Solid State hard drive. The [[Lenovo]] [[ThinkPad#ThinkPad_X300|ThinkPad X300]] also features a built-in 64GB Solid State Drive.
==NAND Flash scalability==
[[Image:NAND_Flash_accelerates_Moore's_Law.JPG|right|thumb|350px|The aggressive trend of process design rule shrinks in NAND Flash memory technology effectively accelerates Moore's Law.]]
Due to its relatively simple structure and high demand for higher capacity, NAND Flash memory is the most aggressively scaled technology among electronic devices. The heavy competition among the top few manufacturers only adds to the aggression. Current projections show the technology to reach ~20 nm by ~2010. While the expected shrink timeline is a factor of two every three years per original version of [[Moore's law]], this has recently been accelerated in the case of NAND flash to a factor of two every two years.
As the feature size of a Flash memory cell reaches the minimum limit (currently estimated ~20 nm), it is likely Flash capacity will be extended by MLC operation or extended 3D stacking.
==See also==
* [[List of emerging technologies]]
* [[CompactFlash]]
* [[Wear levelling]]
* [[DataFlash]]
* [[Open NAND Flash Interface Working Group]]
* [[MoSys, Inc.|1T-FLASH]]
* [[List of flash file systems]]
==References==
{{reflist}}
* [http://news.bbc.co.uk/2/hi/technology/3939333.stm Digital Memories Survive Extremes]
* [http://www.letsgodigital.org/en/flash_memory_cards.html Flash memory database]
===Flash file systems (general references)===
*[http://www.cs.helsinki.fi/u/kraatika/Courses/PIMC2/FlashMemories.pdf Presentation on various Flash File Systems - 9/24/2007]
*[http://www.usenix.org/events//usenix05/tech/general/full_papers/gal/gal.pdf Article regarding various Flash File Systems - 2005 USENIX Annual Conference]
*[http://www.cs.tau.ac.il/~stoledo/Pubs/flash-survey.pdf Survey of various Flash File Systems - 8/10/2005]
==External links==
* [http://www.onfi.org/index.html Open NAND Flash Interface Working Group]
* [http://www2.electronicproducts.com/NAND_vs_NOR_flash_technology-article-FEBMSY1-FEB2002.aspx NAND vs. NOR flash technology:] The designer should weigh the options when using flash memory
* [http://aplawrence.com/Makwana/nonvolmem.html A Nonvolatile Memory Overview]
* [http://computer.howstuffworks.com/flash-memory.htm How Flash Memory Works]
* [http://www.pma-show.com/2006/corporate/sandisk_review/001_sandisk_flash_memory_facility.html SanDisk Flash Memory Plant]
* [http://www.micron.com/products/nand/definingnand What is NAND Flash]
* [http://www.micron.com/products/nand/usingnand NAND Flash Applications]
* [http://www.dataio.com/pdf/NAND/Toshiba/NandDesignGuide.pdf.pdf NAND Flash Applications Design Guide] from Toshiba (explains the low-level details of interfacing with common NAND flash chips)
* [http://www.toshiba.com/taec/components/Generic/Memory_Resources/NANDvsNOR.pdf NAND vs. NOR Flash Memory] from Toshiba
* [http://www.businessreport.com/news/2007/oct/23/samsung-develops-new-flash-tchn1/ Samsung Develops New Flash Memory Chip - AP, October 23, 2007]
* [http://www.numonyx.com Numonyx] - Intel & ST Micro Flash merger
[[Category:Solid-state computer storage media]]
[[Category:Computer memory]]
[[Category:Non-volatile memory]]
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