StrongARM 29445 182439226 2008-01-06T02:11:04Z SmackBot 433328 Date/fix the maintenance tags or gen fixes using [[Project:AutoWikiBrowser|AWB]] {{Unreferenced|date=January 2008}} [[Image:DEC StrongARM.jpg|thumb|DEC StrongARM SA-110 Microprocessor]] The '''StrongARM''' [[microprocessor]] is a faster version of the [[ARM Ltd|Advanced RISC Machines]] [[ARM architecture|ARM]] design. It was created by [[Digital Equipment Corporation]], but later sold to [[Intel]] who continued to manufacture it, before replacing it with the [[XScale]]. == History == The StrongARM was a collaborative project between DEC and ARM to create a faster CPU based on (but not totally compatible with) the existing ARM line. The StrongARM was designed to address the upper-end of the low-power embedded market, where users needed more performance than the ARM could deliver while being able to accept more external support. Targets were devices such as newer [[personal digital assistant]]s and [[set-top box]]es. The project was set up in 1995, and quickly delivered their first design, the '''SA-110'''. This was immediately incorporated into newer versions of the [[Apple Newton]], the [[Acorn Computers|Acorn]] [[Risc PC]], [[Eidos Interactive|Eidos]] Optima video editing system, as well as a number of other products. Digital Semiconductor, DEC's chip division, was later sold to Intel as part of a lawsuit settlement. Intel used the StrongARM to replace their ailing line of RISC processors, the [[Intel i860|i860]] and [[Intel i960|i960]]. The StrongARM SA-1110 was used in the [[Simputer]]. "The Intel StrongARM SA-1110 has been manufacturer discontinued. As a result, Intel StrongARM SA-1110 processor promotional / support information is no longer available on the web."[http://www.intel.com/design/strong/specupdt/278259.htm] The design has been replaced by the [[Intel]] [[XScale]]. == Description == The StrongARM family are faster versions of the existing ARM processors with a somewhat different [[instruction set]]. Clocked at 206MHz they can perform up to 235 [[Million Instructions Per Second|MIPS]] (1.14 MIPS/MHz). They have limited software compatibility with the earlier ARM families due to their separate caches for data and instructions, which causes [[self-modifying code]] to fail. These features were later included in some ARMv4 architectures (notably, the ARM/Texas Instruments ARM925). The StrongARM has an "invalidate cache line" instruction to let the CPU know to reload from main memory. This situation arises rarely in typical software however, and StrongARM is certainly not the only processor to have made such a sacrifice. The [[Motorola]] [[Motorola_68020|68020]], for instance, caused similar compatibility problems for any software designed for the earlier [[Motorola_68000|68000]] and [[Motorola_68010|68010]] models. The StrongARM is designed with slow (and therefore low cost) memory in mind. The StrongARM has a 32 way set associative cache which works on virtual addresses. The high set associativity allows a higher hit rate than competing designs, and the use of virtual addresses allows memory to be simultaneously cached and uncached. A write buffer allows writes to main memory to happen without the CPU stalling, increasing the efficiency of the design. The SA-110 was the first member of the family. Derivatives included the SA-1100 (initially targeted for PDAs) and SA-1500 (initially targeted for set top boxes). The latter processor was designed and manufactured in low volumes by DEC but never put into production by Intel. [[Category:ARM architecture]] [[de:ARM StrongARM]] [[es:StrongARM]] [[fr:StrongARM]] [[it:StrongARM]] [[ja:StrongARM]] [[pl:StrongARM]] [[pt:StrongARM]]