Wafer (electronics) 41860 224257977 2008-07-08T01:03:23Z ItaniuMatrix 2270053 /* Crystalline orientation */ Apostrophe wafer, remove 'can', clear up and link to channelling [[Image:etchedwafer.jpg|thumb|An etched silicon wafer]] [[Image:ICC 2008 Poland Silicon Wafer 1 edit.png|thumb|[[Intel]]'s silicon wafer]] A '''wafer''' is a thin slice of [[semiconductor]] material, such as a [[silicon]] crystal, used in the [[Semiconductor fabrication|fabrication]] of [[integrated circuit]] and other microdevices. The wafer serves as the substrate for [[microelectronic]] devices built in and over the wafer and undergoes many [[microfabrication]] process steps such as [[doping (semiconductors)|doping]] or [[ion implantation]], [[Etching (microfabrication)|etching]], [[Thin-film deposition|deposition]] of various materials, and [[Photolithography|photolithographic]] patterning. Several types of [[solar cell]]s are made from such wafers. A '''solar wafer''' is a circular solar cell made from the entire wafer (rather than cutting into smaller rectangular solar cells). ==Formation== [[Image:Czochralski Process.svg|thumb|right|350px|The [[Czochralski process]].]] [[Image:Wafer_2_Zoll_bis_8_Zoll_2.jpg|thumb|right|200px|2 inch, 4 inch, 6 inch, and 8 inch wafers]] Wafers are formed of highly pure, nearly defect-free single crystalline material. One process for forming crystalline wafers is known as [[Czochralski process|Czochralski growth]] invented by the Polish chemist [[Jan Czochralski]]. In this process, a cylindrical [[ingot]] of high purity crystalline silicon is formed by pulling a seed crystal from a 'melt'. <ref>{{cite book |title=Microelectronic Materials and Processes |last=Levy |first=Roland Albert |year=1989 |pages=1-2 |isbn=0792301544 |url=http://books.google.com/books?id=wZPRPU6ne7UC&pg=PA248&sig=8JXOn_Dc0fPFnyEEkWh53lKWCOk#PPA6,M1 |accessdate=2008-02-23}}</ref> <ref name=Grover/> The ingot is then sliced with an inner diameter diamond coated blade and polished to form wafers. <ref>{{cite book |last=Nishi |first=Yoshio |year=2000|title=Handbook of Semiconductor Manufacturing Technology |pages=67-71 |publisher=CRC Press |isbn=0824787838 |url=http://books.google.com/books?id=Qi98H-iTgLEC&pg=PA70&dq=wafer+flat+and+notch&sig=j6VYgO2HhC_UBhanpRLa9UZC4Pk#PPA71,M1 |accessdate=2008-02-25}}</ref> ==Wafer properties== ===Standard wafer sizes=== Silicon wafers are available in a variety of sizes from 1 inch (25.4 mm) to 11.8 inches (300 mm). <ref>{{citeweb |title=Silicon Wafer |url=http://www.semiwafer.com/products/silicon.htm |accessdate=2008-02-23}}</ref> [[Semiconductor fabrication plant]]s (also known as ''fabs'') are defined by the size of wafers that they are tooled to produce. The size has gradually increased to improve throughput and reduce cost with the current state-of-the-art fab considered to be 300mm (12 inch). * 1 inch. * 2 inch (50.8 mm). Thickness 275 µm. * 3 inch (76.2 mm). Thickness 375 µm. * 4 inch (100 mm). Thickness 525 µm. * 5 inch (125 mm). Thickness 625 µm. * 6 inch (150 mm). Thickness 675 µm. * 8 inch (200 mm). Thickness 725 µm. * 12 inch (300 mm). Thickness 775 µm. Wafers grown using materials other than silicon are generally not available in sizes over 100 mm, and will have different thicknesses than a silicon wafer of the same diameter. Wafer thickness is determined by the mechanical strength of the material used; the wafer must be thick enough to support its own weight without cracking during handling. ====Analytical die count estimation==== For any given wafer diameter ['''d''', ''mm''] and target IC size ['''S''', ''mm<sup>2</sup>''], there is an exact number of integral die pieces that can be sliced out of the wafer. The gross die count ['''A'''] can be estimated by the following expression: <math>A_{gross} = d\pi\left (\frac{d}{4S} - \frac{1}{\sqrt{2S}} \right)</math> Note, that the gross die count does not take into account the die defection loss, various alignment markings and test sites on the wafer. ===Crystalline orientation=== [[Image:Silicon-unit-cell-3D-balls.png|thumb|Diamond Cubic Crystal Structure, Silicon unit cell]] [[Image:Wafer flats convention_v2.svg|thumb|Flats can be used to denote [[doping (semiconductors)|doping]] and [[crystallography|crystallographic]] orientation. Red represents material that has been removed.]] Wafers are grown from crystal having a regular [[crystal structure]], with silicon having a [[diamond cubic]] struture with a lattice spacing of 5.430710 Å (0.5430710 nm). <ref name=HandbookSi>{{cite book |last=O'Mara |first=William C. |year=1990|title=Handbook of Semiconductor Silicon Technology |page =349-352 |publisher=William Andrew Inc. |isbn=0815512376 |url=http://books.google.com/books?id=COcVgAtqeKkC&pg=PA351&dq=Czochralski+Silicon+Crystal+Face+Cubic&lr=&as_brr=3&sig=ht-dgSy1lzBMYC7IXPp9W5QBqYo |accessdate=2008-02-24}}</ref> When cut into wafers, the surface is aligned in one of several relative directions known as crystal orientations. Orientation is defined by the [[Miller index]] with [100] or [111] faces being the most common for silicon. <ref name=HandbookSi/> Orientation is important since many of a single crystal's structural and electronic properties are highly [[anisotropic]]. [[Ion implantation]] depths depend on the wafer's crystal orientation, since each direction offers distinct [[Ion_implantation#Ion_channelling|paths]] for transport. <ref>{{cite book |last=Nishi |first=Yoshio |year=2000 |title=Handbook of Semiconductor Manufacturing Technology |pages=108-109 |publisher=CRC Press |isbn=0824787838 |url=http://books.google.com/books?id=Qi98H-iTgLEC&pg=PA70&dq=wafer+flat+and+notch&sig=j6VYgO2HhC_UBhanpRLa9UZC4Pk#PPA71,M1 |accessdate=2008-02-25}}</ref> Wafer [[cleavage (crystal)|cleavage]] typically occurs only in a few well-defined directions. Scoring the wafer along cleavage planes allows it to be easily diced into individual chips ("[[Die (integrated circuit)|die]]s") so that the billions of individual [[Electronic component|circuit elements]] on an average wafer can be separated into many individual circuits. ===Wafer flats and orientation notches=== Wafers under 200 mm generally have ''flats'' cut into one or more sides indicating [[crystallography|crystallographic]] planes of high symmetry (usually the {110} face) and, in old-fashioned wafers (those below about 100 mm diameter), the wafer's orientation and doping type (see illustration for conventions). Modern wafers use a notch to convey this information, in order to waste less material <ref>{{citeweb |title=Wafer Flats |url=http://www.tf.uni-kiel.de/matwis/amat/elmat_en/kap_5/illustr/i5_2_4.html |accessdate=2008-02-23}}</ref>. ===Impurity doping=== Silicon wafers are generally not 100% pure silicon, but are instead formed with an initial impurity [[Doping (semiconductors)|doping]] concentration between 10<sup>13</sup> and 10<sup>16</sup> per cm<sup>3</sup> of [[boron]], [[phosphorus]], [[arsenic]], or [[antimony]] which is added to the melt and defines the wafer as either bulk n-type or p-type.<ref>{{cite book |last=Widmann |first=Dietrich |year=2000 |title=Technology of Integrated Circuits |pages=39 |publisher=Springer |isbn=ISBN 3540661999 |url=http://books.google.com/books?id=uYNn1N6YSwQC&pg=PA39&dq=Czochralski+Doping+Silicon&as_brr=3&sig=xRljFzhA9fSbRddEc3Gg3-Wht2U |accessdate=2008-02-24}}</ref> However, compared with single-crystal silicon's atomic density of 5×10<sup>22</sup> atoms per cm<sup>3</sup>, this still gives a purity greater than 99.9999%. The wafers can also be initially provided with some interstitial oxygen concentration. Carbon and metallic contamination are kept to a minimum. <ref>{{cite book |title=Microelectronic Materials and Processes |last=Levy |first=Roland Albert |year=1989 |pages=6-7, 13 |isbn=0792301544 |url=http://books.google.com/books?id=wZPRPU6ne7UC&pg=PA248&sig=8JXOn_Dc0fPFnyEEkWh53lKWCOk#PPA1,M1 |accessdate=2008-02-23}}</ref> [[Transition metal]]s, in particular, must be kept below parts per billion concentrations for electronic applications. <ref>{{cite book |title=The Materials Science of Semiconductors|last=Rockett |first=Angus |year=2008 |pages=13 |isbn=9780387256535}}</ref> ==Compound semiconductors== While silicon is the most prevalent type of wafer used in the electronics industry, other compound [[List of semiconductor materials|III-V]] or [[List of semiconductor materials|II-VI]] type wafers have also been employed. [[Gallium arsenide]] (GaAs) wafers are one common III-V semiconductor material which can be produced using the Czochralski process. <ref name=Grover> {{cite book |title=Microelectronic Materials |last=Grovenor |first= C. |year= 1989 |isbn=0852742703 |publisher=CRC Press |pages=113-123 |url=http://books.google.com/books?id=Ecl_mnz1xcUC&pg=PA122&dq=GaAs+Wafer+Manufacture&as_brr=3&sig=eu7LVmemnCFtCk9s0Cmo4HK4OwM#PPA113,M1 |accessdate=2008-02-25}}</ref> ==See also== *[[Mono-crystalline silicon]] *[[Silicon on insulator]] (SOI) wafers *[[Solar panel]] *[[RCA clean]] ==References== {{Commons2|Wafers}} {{reflist}} [[Category:Semiconductor device fabrication]] [[de:Wafer]] [[es:Oblea (electrónica)]] [[fr:Wafer]] [[ko:웨이퍼]] [[id:Wafer]] [[it:Wafer (elettronica)]] [[nl:Wafer]] [[ja:ウェハー]] [[pt:Wafer (eletrônica)]] [[ru:Подложка]] [[sk:Wafer]] [[fi:Piikiekko]] [[sv:Kiselplatta]] [[vi:Đĩa bán dẫn]] [[uk:Підкладка (мінералогія)]] [[zh:晶圓]]