BRA a-state a-init LDA sort0 OUT a-state INP STO entry BRZ a-init LDA entry SUB ent2 BRZ b-init BRA a-init b-init LDA sort0 OUT b-state INP STO entry BRZ b-init LDA entry SUB ent2 BRZ c-init LDA sort1 OUT BRA a-state c-init LDA sort0 OUT c-state INP STO entry BRZ c-init LDA entry SUB ent2 BRZ d-init LDA sort2 OUT BRA a-state d-init LDA sort0 OUT d-state INP STO entry BRZ d-init LDA entry SUB ent1 BRZ c-s001-a LDA sort4 OUT BRA a-state c-s001-a LDA sort3 OUT BRA a-state ent0 DAT 0 ent1 DAT 1 ent2 DAT 2 sort0 DAT 0 sort1 DAT 1 sort2 DAT 2 sort3 DAT 3 sort4 DAT 4 zero DAT 0 entry DAT 0