Minimizing Sensitivity to Clock Skew Variations Using Level Sensitive Latches
F. R. Boyer, E. M. Aboulhamid, and Y. Savaria.
Submitted to ECCTD'01: European Conference on Circuit Theory and Design, Espoo, Finland, August 28-31, 2001.
PDF version of this paper.
An Efficient Verification Method for a Class of Multi-phase
Sequential Circuits
F. R. Boyer, E. M. Aboulhamid, and Y. Savaria.
Presented at ICECS'2K: The 7th IEEE International Conference on Electronics, Circuits & Systems, Portemilio Hotel, Jounieh, Kaslik, Lebanon, Decembre 17-20, 2000.
PDF version of this paper.
Optimal design of synchronous circuits using software
pipelining techniques
Extended version:
F. R. Boyer, E. M. Aboulhamid, Y. Savaria, and Michel BoyerPrevious versions: (all included in the above version)
Published in ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 6, Number 4 (October, 2001).
PDF version of this paper.
Please note that this material is coyrighted by the ACM.
F. R. Boyer, E. M. Aboulhamid, Y. Savaria, and I. E. Bennour.
Presented at 1998 IEEE/ACM International Workshop on Logic Synthesis, Granlibakken Resort, Lake Tahoe, California, June 7-10, 1998.
Also presented at 1998 International Conference on Computer Design, Marriott Hotal at the Capital, Austin, Texas, October 5-7, 1998.PDF versions of this paper: IWLS'98 (with the proofs and extensions), ICCD'98 (short version).
Please note that this material is coyrighted by the IEEE.
VIP: An FPGA-based processor for Neural Networks and image processing
J. Cloutier, Eric Cosatto, Steven Pigeon, F. R. Boyer, and P. Y. Simard.
Fifth International Conference on Microelectronics for Neural Networks and Fuzzy Systems (MicroNeuro'96), Lausanne, Switzerland, February 1996.
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